The invention relates to a high-speed cache which can improve the execute efficiency of processor, wherein when one high-speed cache is demanded to be received, and the logic unit of cache judges if said received cache demands to generate one hit on high-speed cache; if it demands, serving the demand of high-speed cache; or else, if received cache demands one miss on the high-speed cache, storing the information relative to the demand of received high-speed cache into one miss demand list; the miss read demand should be stored in the miss read demand list and the miss write demand is stored in the miss write demand list. |