A data transfer device, which comprises an input/output reception buffer (15), an input/output transmission buffer (14), a write data buffer (13), a read data buffer (12), a control information table (11a), a write data storing process section (17), a write data transmission section (34), a read data buffer storing process section (33), an input/output transmission buffer storing process section (18) and a control section (16) that executes an access control for controlling the access to the memory by the write data transmission section(34) and the read data buffer storing process section (33) based on a control information table (11). Thereby, a configuration optimum for both protocols of the memory bus and the input/output bus is obtained and the out-of-order execution is also achievable. |