The present invention is one clock synchronizer for transmitting pulse signal from the first circuit block operating in the first clock signal to the second circuit block operating in the second clock signal. The clock synchronizer includes one first logic gate and one first trigger operating on the first clock, one second logic gate and one second trigger operating on the second clock, one first synchronizing circuit with the second clock signal in treating the output of the first trigger, and one second synchronizing circuit with the firs clock signal in treating the output of the first synchronizing circuit. The output of the first logic gate is fed to the asymmetrical input of the first trigger, the output of the second synchronizing circuit is used as one input of the first logic gate, the outputs of the first synchronizing circuit and the second trigger are coupled to the input of the second logic gate. The present invention has no need of limiting the period ratio between the two clock signals. |