A flash memory device comprises a plurality of plains each including a plurality of memory cell blocks, page buffers each latching an input data bit to be output to its corresponding plain or latching an output data bit to be received from the corresponding plain, cache buffers each storing an input or output data bits in response to one of cache input control signals and each transferring the stored data bit to the page buffer or an external device in response to one of cache output control signals, and a control logic circuit generating the cache input and output control signals in response to command and chip enable signals containing plural bits. The program and read operations for the plural plains are conducted simultaneously in response to the chip enable signal containing the plural bits, which increases an operation speed and data throughput processed therein. |