A process for integrally fabricating a memory cell capacitor and a logic device is disclosed. A first conductive layer and second conductive layer are formed above a semiconductor substrate with a logic region and memory cell region. A first photoresist layer is formed to cover the logic region, and expose an inter-metal dielectric layer adjacent to the second conductive layer in the memory cell region. The exposed inter-metal dielectric layer is etched off to form an opening adjacent to the second conductive layer. A capacitor dielectric layer and third conductive layer are formed on inner walls of the opening to constitute a metal-insulator-metal capacitor. |